PCI-SIG Releases PCIe 8.0 Draft 0.5 with 1 TB/s Bandwidth

The PCI-SIG announced the release of draft 0.5 of the PCIe 8.0 specification this week, marking a key milestone in developing the next generation of high-speed interconnect technology for computers and data centers.

The draft outlines a maximum raw data rate of 256 GT/s using PAM4 signaling, delivering up to 1 TB/s of bidirectional bandwidth in x16 lane configurations. This represents eight times the bandwidth of PCIe 5.0, the current standard in many consumer systems. Bandwidth scales across configurations as follows: 64 GB/s for x1, 128 GB/s for x2, 256 GB/s for x4, 512 GB/s for x8, and 1,024 GB/s for x16. For context, a single x1 lane in PCIe 8.0 matches the full x16 bandwidth of PCIe 4.0, while x2 equals PCIe 5.0's x16 capacity and x4 aligns with PCIe 6.0's maximum.

PCIe 8.0 incorporates forward error correction, Flit Mode encoding, and other protocol enhancements to optimize latency, reliability, and power efficiency while ensuring backward compatibility with prior generations. The specification also signals a shift in physical design, as the group evaluates new connector technologies. Current copper-based connectors, which support up to 16 lanes between components like...